The present invention relates generally to application specific integrated circuits (ASICs) and specifically to providing a Field Programmable Gate. Array (FPGA) cell within an ASIC for configuring the ASIC.
Many integrated circuits, particularly software programmable processor chips, require initialization procedures in order to configure the chip to perform specific functions correctly. For example, both the on-chip memory (OCM) controller function and the universal interrupt controller (UIC) on a PowerPC processor, part number PPC405GP, manufactured by IBM Corporation, require initialization after processor reset, for best performance in the case of the OCM and for proper operation in case of the UIC. Other PowerPC processor on-chip functions, such as the UART controller, may require initialization depending upon the application. Currently each user of the PowerPC processor must code these required initialization routines in software which can be time consuming and difficult to debug. Initializing the OCM for both Instruction-side and Data-side operations is a 12-step process. Initializing the UIC is more complex and varies depending on the application. Initialization of external system components or system-specific chip facilities must also be performed in addition to the basic initialization required for the processor.
Accordingly, what is needed is a system and method for initializing the chip to allow for proper configuration within the complexity of existing conventional initialization procedures. The system should be cost effective and easily implemented in existing circuits. The present invention addresses such a need.
An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell.
In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization. Access to these registers can be controlled by a simple muxing structure that allows the FPGA to have direct access to the registers when the chip initialization sequence takes place (Chip_Init signal is asserted) and allows the processor bus to have access after initialization is complete (Chip_Init signal is de-asserted)